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GS8170DW36AGC-250I Datasheet(PDF) 1 Page - GSI Technology

Part No. GS8170DW36AGC-250I
Description  18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM
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Maker  GSI [GSI Technology]
Homepage  http://www.gsitechnology.com
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GS8170DW36/72AC-350/333/300/250
18Mb
Σ1x1Dp CMOS I/O
Double Late Write SigmaRAM™
250 MHz–350 MHz
1.8 V VDD
1.8 V I/O
209-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.04 4/2005
1/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAM
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
• Pb-Free 209-bump BGA package available
SigmaRAM Family Overview
GS8170DW36/72A SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The
ΣRAM
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Bottom View
Parameter Synopsis
Key Fast Bin Specs
Symbol
- 350
Cycle Time
tKHKH
2.86 ns
Access Time
tKHQV
1.7 ns




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