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GS8330LW36C Datasheet(PDF) 6 Page - GSI Technology |
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GS8330LW36C Datasheet(HTML) 6 Page - GSI Technology |
6 / 30 page Rev: 1.00 6/2003 6/30 © 2003, GSI Technology, Inc. Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative. Preliminary GS8330LW36/72C-250/200 Late Write In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT SRAMs. Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Example of x36 Byte Write Truth Table Function W Ba Bb Bc Bd Read H XXX X Write Byte A L L H H H Write Byte B L H L H H Write Byte C L H H L H Write Byte D L H H H L Write all Bytes L L L L L Write Abort L H H H H SigmaRAM Late Write with Pipelined Read Key QD QA DC CQ Read Read CDE ADV Read Deselect Write Hi-Z F Access CK Address A XX /E1 /W DQ |
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