4/11/01; v.0.9

Alliance Semiconductor

P. 8 of 18

AS4C4M4F0

AS4C4M4F1

®

Notes

3

An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal

refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after

extended periods of bias without clocks (greater than 8 ms).

4

(max)

6

7

8

Assumes three state test load (5 pF and a 380

rising edge of RAS or CAS, whichever occurs last.

selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.

12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.

15 These parameters are sampled and not 100% tested.

16 These characteristics apply to AS4C4M4F0 5V devices.

AC test conditions

Key to switching waveforms

- Input rise and fall times: 2 ns

100 pF*

R2 = 295

Ω

R1 = 828

Ω

GND

+5V

Figure A: Equivalent output load

*including scope

and jig capacitance

*including scope

and jig capacitance

50 pF*

R2 = 295

Ω

R1 = 828

Ω

GND

+3.3V

Figure B: Equivalent output load

(AS4LC4M4E0)

(AS4C4M4E0)

Undefined output/don’t care

Falling input

Rising input