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GS88136T-11I Datasheet(PDF) 8 Page - GSI Technology

Part # GS88136T-11I
Description  512K x 18, 256K x 36 ByteSafe??8Mb Sync Burst SRAMs
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Manufacturer  GSI [GSI Technology]
Direct Link  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS88136T-11I Datasheet(HTML) 8 Page - GSI Technology

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Rev: 1.11 9/2000
8/33
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88118/36T-11/11.5/100/80/66
Note:
There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above table.
Burst Counter Sequences
BPR 1999.05.18
Byte Write Truth Table
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00


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