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GS816273CGC-300I Datasheet(PDF) 6 Page - GSI Technology |
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GS816273CGC-300I Datasheet(HTML) 6 Page - GSI Technology |
6 / 28 page Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H Interleaved Burst Power Down Control ZZ L or NC Active H Standby, IDD = ISB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance Control ZQ L High Drive (Low Impedance) H or NC Low Drive (High Impedance) GS816273CC-333/300/250 Preliminary Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01a 6/2006 6/28 © 2005, GSI Technology Note: There are pull-up devices on the ZQ and SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 Burst Counter Sequences BPR 1999.05.18 |
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