TABLE 1. Power Down Modes

CE pin

RF_PD Bit

Mode

HIGH

0

Active

HIGH

1

Not Active

LOW

0

Not Active

LOW

1

Not Active

VCO SELECTION

The RF_SEL bit must be used to select the RF VCO output.

When using the LMX2515LQ0701 the RF_SEL bit must be

set to "0". When using the LMX2515LQ1321 the RF_SEL bit

must be set to "1".

TABLE 2. VCO Selection

RF_SEL Bit

Mode

0

LMX2515LQ0701

1

LMX2515LQ1321

LOCK DETECT MODE

The LD output can be used to indicate the lock status of the

PLL. Bit 6 in Register R1 determines the signal that appears

on the LD pin. When the PLL is not locked, the LD pin

remains LOW. After obtaining phase lock, the LD pin will

have a logical HIGH level. The LD output is always low when

the LD register bit is 0 and in power down mode.

TABLE 3. Lock Detect Modes

LD Bit

Mode

0

Disable (GND)

1

Enable

TABLE 4. Lock Detect Logic

RF-PLL Section

LD Output

Locked

HIGH

Not Locked

LOW

four or more consecutive cycles.

Note 15: Phase Error is measured on leading edge. Only errors greater than

20068808

FIGURE 2. Lock Detect Timing Diagram Waveform (Notes 13, 14, 15, 16, 17)

www.national.com

10