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HY57V561620CLT-H Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HY57V561620CLT-H Datasheet(HTML) 7 Page - Hynix Semiconductor |
7 / 12 page HY57V561620C(L)T(P) Rev. 0.5 / June 2004 7 AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate Parameter Symbol -6 -7 -K -H -8 -P -S Unit Note Min Max Min Max Min Max Min Max Min Max Min Max Min Max System Clock Cycle Time CAS Latency = 3 tCK3 6 1000 7 1000 7.5 1000 7.5 1000 8 1000 10 1000 10 1000 ns CAS Latency = 2 tCK2 7.5 10 7.5 10 10 10 12 ns Clock High Pulse Width tCHW 2.5 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 Clock Low Pulse Width tCLW 2.5 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 Access Time From Clock CAS Latency = 3 tAC3 - 5.4 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns 2 CAS Latency = 2 tAC2 - 6 - 6 - 5.4 - 6 - 6 - 6 - 6 ns Data-Out Hold Time tOH 2.7 - 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Address Setup Time tAS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Address Hold Time tAH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command Setup Time tCS 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command Hold Time tCH 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns CLK to Data Output in High-Z Time CAS Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3636 ns CAS Latency = 2 tOHZ2 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3636 ns |
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