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74AHCT139D Datasheet(PDF) 10 Page - NXP Semiconductors |
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74AHCT139D Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 1999 Sep 01 10 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74AHC139; 74AHCT139 AC WAVEFORMS Fig.5 The address input (nAn) to output (nYn) propagation delays. FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC handbook, halfpage MNA469 tPHL VI GND VOH VOL tPLH VM (1) VM (1) nAn INPUT nYn OUTPUT Fig.6 The enable input (nE) to output (nYn) propagation delays. FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC handbook, halfpage MNA470 tPHL VI GND VOH VOL tPLH VM (1) VM (1) nE INPUT nYn OUTPUT Fig.7 Load circuitry for switching times. handbook, full pagewidth open GND VCC VCC VI VO MNA219 D.U.T. CL RT 1000 Ω PULSE GENERATOR S1 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. (See Chapter “AC characteristics” for values). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. |
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