+3.3V, 10.7Gbps 1:16 Deserializer

with LVDS Outputs

6

_______________________________________________________________________________________

Detailed Description

The MAX3950 deserializer implements a shift-register-

based demultiplexer to convert 9.953Gbps serial data

to 16-bit-wide, 622.08Mbps parallel data (Figure 4).

The allocation of the serial input bits to the parallel

LVDS outputs is displayed in Figure 5.

Applications Information

Low-Voltage Differential-Signal

Outputs

The MAX3950 features LVDS outputs for interfacing

with high-speed digital circuitry. This LVDS implementa-

tion is based on the IEEE 1596.3 LVDS reduced-range

link specification and is compatible with OIF 1999.102.

Note that the PCLK polarity on the MAX3950 is inverted

relative to OIF 1999.102, so that PCLK+ is equivalent to

RXCLK_N and PCLK- is equivalent to RXCLK_P.

low-voltage swings to achieve fast transition times, min-

imize power dissipation, and improve noise immunity.

The parallel clock and data LVDS outputs (PCLK+,

PCLK-, PD_+, PD_-) require 100

Ω differential DC termi-

nation between the inverting and noninverting outputs

for proper operation. Do not terminate these outputs to

ground. For more information on interfacing with the

LVDS outputs, refer to Maxim Application Note HFAN-

1.0: Interfacing Between CML, PECL, and LVDS.

PIN

NAME

FUNCTION

15

PCLK+

Positive Parallel Clock Output, 622.08MHz, LVDS.

19, 21, 23, 27, 29, 38,

40, 44, 46, 48, 56, 58,

62, 64, 66, 3

PD0- to

PD15-

Negative Parallel Data Output, 622.08Mbps, LVDS.

20, 22, 24, 28, 30, 39,

41, 45, 47, 49, 57, 59,

63, 65, 67, 4

PD0+ to

PD15+

Positive Parallel Data Output, 622.08Mbps, LVDS.

EP

Exposed

Pad

Ground. This must be soldered to the circuit board ground for proper thermal and

electrical operation. See Layout Considerations.

CP

Corner

Pins

N.C. Not Connected. Ensure that the solder mask is located below them so that

unintentional connections do not occur.

Pin Description (continued)

CML INPUT

CML INPUT

D FLIP-FLOP

DELAY

DIVIDE BY 4

CLK

DATA

4-BIT SHIFT

REGISTER

4-BIT SHIFT

REGISTER

4-BIT SHIFT

REGISTER

4-BIT SHIFT

REGISTER

CLK

DIVIDE BY 4

DATA

MAX3950

Figure 4. Functional Block Diagram