AT28C16

3

Device Operation

READ: The AT28C16 is accessed like a Static RAM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in a high

impedance state whenever CE or OE is high. This dual line

control gives designers increased flexibility in preventing

bus contention.

BYTE WRITE: Writing data into the AT28C16 is similar to

writing into a Static RAM. A low pulse on the WE or CE

input with OE high and CE or WE low (respectively) ini-

tiates a byte write. The address location is latched on the

last falling edge of WE (or CE); the new data is latched on

the first rising edge. Internally, the device performs a self-

clear before write. Once a byte write has been started, it

will automatically time itself to completion. Once a pro-

gramming operation has been initiated and for the duration

of t

tion.

FAST BYTE WRITE: The AT28C16E offers a byte write

time of 200

µs maximum. This feature allows the entire

device to be rewritten in 0.4 seconds.

DATA POLLING: The AT28C16 provides DATA POLLING

to signal the completion of a write cycle. During a write

cycle, an attempted read of the data being written results in

the complement of that data for I/O

indeterminate). When the write cycle is finished, true data

appears on all outputs.

WRITE PROTECTION: Inadvertent writes to the device

are protected against in the following ways: (a) V

CC

sense—if V

inhibited; (b) V

3.8V the device will automatically time out 5 ms (typical)

before allowing a byte write; and (c) write inhibit—holding

any one of OE low, CE high or WE high inhibits byte write

cycles.

CHIP CLEAR: The contents of the entire memory of the

AT28C16 may be set to the high state by the CHIP CLEAR

operation. By setting CE low and OE to 12 volts, the chip is

cleared when a 10 msec low pulse is applied to WE.

DEVICE ID E N TIF I CAT IO N: An extr a 32 bytes of

EEPROM memory are available to the user for device iden-

tification. By raising A9 to 12

± 0.5V and using address

locations 7E0H to 7FFH the additional bytes may be written

to or read from in the same manner as the regular memory

array.