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AT49BV321-90TI Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT49BV321-90TI Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 30 page 8 AT49BV/LV320(T)/321(T) 1494H–FLASH–01/03 PRODUCT IDENTIFICATION: The product identification mode identifies the device and man- ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see “Operating Modes” on page 18 (for hardware operation) or “Software Product Identification Entry/Exit” sections on page 25. The manufacturer and device codes are the same for both modes. 128-BIT PROTECTION REGISTER: The AT49BV/LV32X(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the “Command Definition in Hex” table on page 12. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the “Command Definition in Hex” table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register Addressing Table” on page 13 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. RDY/BUSY: For the AT49BV/LV321(T), an open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. Please see “Status Bit Table” on page 11 for more details. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the AT49BV/LV32X(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before pro- gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) Program inhibit: VPP is less than VILPP.(f) VPP power-on delay: once VPP has reached 1.65V, program and erase operations are inhibited for 100 ns. INPUT LEVELS: While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE,CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC +0.6V. OUTPUT LEVELS: For the AT49BV/LV320(T), output high levels (VOH) are equal to VCCQ - 0.2V (not VCC). For 2.65V - 3.6V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V out- put levels, VCCQ must be regulated to 2.0V ± 10%, while VCC must be regulated to 2.65V - 3.0V (for minimum power). |
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