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OP16AJMDA Datasheet(PDF) 2 Page - Analog Devices |
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OP16AJMDA Datasheet(HTML) 2 Page - Analog Devices |
2 / 12 page REV. A –2– OP15/OP17–SPECIFICATIONS OP15A, OP15E OP15F OP15G OP17A, OP17E OP17F OP17G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Input Offset Voltage VOS RS = 50 W 0.2 0.5 0.4 1.0 0.5 3.0 mV Input Offset Current IOS OP15 TJ = 25 ∞C1 310 620 12 50 pA Device Operating 5 22 10 40 20 100 pA OP17 TJ = 25 ∞C1 310 620 12 50 pA Device Operating 5 25 10 50 20 125 pA Input Bias Current IB OP15 TJ = 25 ∞C1 ±15 ±50 ±30 ±100 ±60 ±200 pA Device Operating ±18 ±110 ±40 ±200 ±80 ±400 pA OP17 TJ = 25 ∞C1 ±15 ±50 ±30 ±100 ±60 ±200 pA Device Operating ±20 ±130 ±40 ±250 ±80 ±500 pA Input Resistance RIN 10 12 10 12 10 12 W Large-Signal AVO RL ≥ 2 kW 100 240 75 220 50 200 V/mV Voltage Gain VO = ±10 V Output Voltage VO RL = 10 k W±12 ±13 ±12 ±13 ±12 ±13 V Swing RL = 2 k W±11 ±12.7 ±11 ±12.7 ±11 ±12.7 V Supply Current ISY OP15 2.7 4.0 2.7 4.0 2.8 5.0 mA OP17 4.6 7.0 4.6 7.0 4.8 8.0 mA Slew Rate 2 SR AVCL = 1, OP15 10 13 7.5 11 5 9 V/ ms AVCL = 5, OP17 45 60 35 50 25 40 V/ ms Gain Bandwidth 3 GBW OP15 4.0 6.0 3.5 5.7 3.0 5.4 MHz Product OP17 20 30 15 28 11 26 MHz Closed-Loop CLBW AVCL = 1, OP15 14 13 12 MHz Bandwidth AVCL = 5, OP17 11 10 9 MHz Settling Time tS OP15 To 0.01% 4.5 4.5 4.7 ms To 0.05% 1.5 1.5 1.6 ms To 0.10% 1.2 1.2 1.3 ms OP17 To 0.01% 1.5 1.5 1.6 ms To 0.05% 0.7 0.7 0.8 ms To 0.10% 0.6 0.6 0.7 ms Input Voltage Range IVR ±10.5 ±10.5 ±10.3 V Common-Mode CMRR VCM = ±10.5 V 86 100 86 100 dB Rejection Ratio VCM = ±10.3 V 82 96 dB Power Supply PSRR VS = ±10 V to ±18 V 10 5110 51 mV/V Rejection Ratio VS = ±10 V to ±18 V 10 80 mV/V Input Noise en fO = 100 Hz 20 20 20 nV/ ÷Hz Voltage Density fO = 1 kHz 15 15 15 nV/ ÷Hz Input Noise in fO = 100 Hz 0.01 0.01 0.01 pA/ ÷Hz Current Density fO = 1 kHz 0.01 0.01 0.01 pA/ ÷Hz Input Capacitance CIN 33 3 pF NOTES 1Input bias current is specified for two different conditions. The T J = 25 ∞C specification is with the junction at ambient temperature; the device operating specification is with the device operating in a warmed-up condition at 25 ∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the curves of IB versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and IOS are measured at VCM = 0. 2Settling time is defined here for a unity gain inverter connection using 2 k W resistors. It is the time required for the error voltage (the voltages at the inverting input pit on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit. 3Sample tested. 4Settling time is defined here for A V = –5 connection with RF = 2 k W. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit. ELECTRICAL CHARACTERISTICS (@ V S = 15 V, TA = 25 C, unless otherwise noted) |
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