Philips Semiconductors

Product specification

74ALS86

Quad 2-input exclusive-OR gate

2

1996 Jul 01

853–0596 01670

DESCRIPTION

The 74ALS86 contain four independent 2-input Exclusive-OR gates.

A common application is a true/complement element. If one input is

held Low, the signal on the other input will be reproduced in true

form at the output. If one input is held High, the signal on the other

input will be reproduced inverted at the output.

TYPE

TYPICAL

PROPAGATION DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74ALS86

6.0ns

3.9mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

DRAWING

NUMBER

14-pin plastic DIP

74ALS86N

SOT27-1

14-pin plastic SO

74ALS86D

SOT108-1

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

1A

1B

1Y

2A

2B

2Y

GND

3Y

3A

3B

4Y

4A

4B

SC00010

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74ALS (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

nA, nB

Data inputs

1.0/1.0

20

µA/0.1mA

nY

Data outputs

20/80

0.4mA/8mA

NOTE:

One (1.0) ALS unit load is defined as: 20

µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

GND = Pin 7

1245

9

10

12

13

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

36

8

11

SC00011

IEC/IEEE SYMBOL

1

2

4

5

9

10

12

13

3

6

8

11

SC00037

=1

LOGIC DIAGRAM

GND = Pin 7

1A

1B

2A

2B

3A

3B

4A

4B

1Y

2Y

3Y

4Y

3

6

8

11

1

2

4

5

9

10

12

13

SC00038

FUNCTION TABLE

INPUTS

OUTPUT

nA

nB

nY

L

L

L

L

H

H

H

L

H

H

H

L

H = High voltage level

L

= Low voltage level