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CY7C1327B Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C1327B
Description  256K x 18 Synchronous-Pipelined Cache RAM
Download  17 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1327B Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C1327B
Document #: 38-05140 Rev. **
Page 3 of 17
Pin Configurations (continued)
2
3
4
567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
NC
DQb
DQb
DQb
DQb
AA
A
A
ADSP
VDDQ
CE2
A
NC
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VSS
NC
NC
NC
NC
A
A
NC
VDDQ
VDDQ
VDDQ
ANC
A
A
CE3
A
A
A
A
A
A
A0
A1
DQa
DQb
NC
NC
DQa
NC
DQa
DQa
NC
NC
DQa
NC
DQa
NC
DQa
NC
DQa
VDD
NC
DQb
NC
VDD
DQb
NC
DQb
NC
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
MODE
DQPb
DQPa
Vss
BWb
NC
VDD
NC
BWa
NC
BWE
Vss
ZZ
119-Ball BGA
A
Pin Definitions
Name
I/O
Description
A[17:0]
Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the
2-bit counter.
BW[1:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[1:0] and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.


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