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CY7C1325B-100BGC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C1325B-100BGC
Description  256K x 18 Synchronous 3.3V Cache RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1325B-100BGC Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C1325B
3
Pin Configurations (continued)
2
34
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
NC
DQb
DQb
DQb
DQb
AA
A
A
ADSP
VDDQ
CE2
A
NC
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VSS
NC
NC
NC
NC
A
A
NC
VDDQ
VDDQ
VDDQ
ANC
A
A
CE3
A
A
A
A
A
A
A0
A1
DQa
DQb
NC
NC
DQa
NC
DQa
DQa
NC
NC
DQa
NC
DQa
NC
DQa
NC
DQa
VDD
NC
DQb
NC
VDD
DQb
NC
DQb
NC
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
MODE
DQPb
DQPa
Vss
BWb
NC
VDD
NC
BWa
NC
BWE
Vss
ZZ
119-Ball BGA
A
Pin Descriptions
Name
I/O
Description
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
A[1:0]
Input-
Synchronous
A1, A0 address inputs, These inputs feed the on-chip burst counter as the LSBs as well as being
used to access a particular memory location in the memory array.
A[17:2]
Input-
Synchronous
Address Inputs used in conjunction with A[1:0] to select one of the 256K address locations. Sampled
at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active
LOW.
BWS[1:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
rising edge. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1. See Write Cycle
Descriptions table for further details.
ADV
Input-
Synchronous
Advance input used to advance the on-chip address counter. When LOW the internal burst counter
is advanced in a burst sequence. The burst sequence is selected using the MODE input.
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
GW
Input-
Synchronous
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
a global write, independent of the state of BWE and BWS[1:0]. Global writes override byte writes.
CLK
Input-Clock
Clock input. Used to capture all synchronous inputs to the device.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. CE1 gates ADSP.


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