CY7C1338B-100AC datasheet(11/18 Pages) CYPRESS

Part #	CY7C1338B-100AC

Description	128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1338B

Document #: 38-05143 Rev. **

Page 11 of 18

Read Cycle Timing[13, 15]

Note:

15. RDx stands for Read Data from Address X.

Timing Diagrams (continued)

ADSP

CLK

ADSC

ADV

ADD

CE1

OE

GW

WE

CE2

CE3

2a

2c

1a

Data Out

tCYC

tCH

tCL

tADS

tADH

tADS

tADH

tADVS

tADVH

RD1

RD2

RD3

tAH

tAS

tWS

tWH

tWS

tCES

tCEH

tCES

tCEH

tCES

tCEH

tCDV

tEOV

2b

2c

2d

3a

1a

tOEHZ

tDOH

tCLZ

tCHZ

Single Read

Burst Read

Unselected

ADSP ignored with CE1 inactive

Suspend Burst

CE1 masks ADSP

= DON’T CARE

= UNDEFINED

Pipelined Read

ADSC initiated read

Unselected with CE2

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CY7C1338B-100AC Datasheet(PDF) 11 Page - Cypress Semiconductor

CY7C1338B-100AC Datasheet(HTML) 11 Page - Cypress Semiconductor

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