5 / 37 page
CY7C0430BV
CY7C04312BV
CY7C04314BV
Document #: 38-06027 Rev. *A
Page 5 of 37
Pin Configuration
272-ball Grid Array (BGA)
Top View
Notes:
5.
Central Leads are for thermal dissipation only. They are connected to device VSS.
6.
Pin is VSS for CY7C04312BV and CY7C04314BV devices.
7.
Pin is NC for CY7C04312BV and CY7C04314BV devices.
8.
Pin is VSS for CY7C04312BV and CY7C04314BV devices.
9.
Pin is VSS for CY7C04314BV devices.
123456789
10
11
12
13
14
15
16
17
18
19
20
A
LB
P1
I/O17
P2
I/O15
P2
I/O13
P2
I/O11
P2
I/O9
P2
I/O16
P1
I/O14
P1
I/O12
P1
I/O10
P1
I/O10
P4
I/O12
P4
I/O14
P4
I/O16
P4
I/O9
P3
I/O11
P3
I/O13
P3
I/O15
P3
I/O17
P3
LB
P4
B
VDD1
UB
P1
I/O16
P2
I/O14
P2
I/O12
P2
I/O10
P2
I/O17
P1
I/O13
P1
I/O11
P1
TMS
TDI
I/O11
P4
I/O13
P4
I/O17
P4
I/O10
P3
I/O12
P3
I/O14
P3
I/O16
P3
UB
P4
VDD1
C
A14
P1[9]
A15
P1[8]
CE1
P1
CE0
P1
R/W
P1
I/O15
P1
VSS2
VSS2
I/O9
P1
TCK
TDO
I/O9
P4
VSS2
VSS2
I/O15
P4
R/W
P4
CE0
P4
CE1
P4
A15
P4[8]
A14
P4[9]
D
VSS1
A12
P1
A13
P1
OE
P1
VDD2
VSS2
VSS2
VDD2
VDD
VSS
VSS
VDD
VDD2
VSS2
VSS2
VDD2
OE
P4
A13
P4
A12
P4
VSS1
E
A10
P1
A11
P1
MKRD
P1
CNTRD
P1[6]
CNTRD
P4 [6]
MKRD
P4
A11
P4
A10
P4
F
A7
P1
A8
P1
A9
P1
CNTINT
P1[7]
CNTINT
P4[7]
A9
P4
A8
P4
A7
P4
G
VSS1
A5
P1
A6
P1
CNTINC
P1[6]
CNTINC
P4[6]
A6
P4
A5
P4
VSS1
H
A3
P1
A4
P1
MKLD
P1
CNTLD
P1[6]
CNTLD
P4[6]
MKLD
P4[6]
A4
P4
A3
P4
J
VDD1
A1
P1
A2
P1
VDD
GND[5]
GND[5]
GND[5]
GND[5]
VDD
A2
P4
A1
P4
VDD1
K
A0
P1
INT
P1
CNTRST
P1[6]
CLK
P1
GND[5]
GND[5]
GND[5]
GND[5]
CLK
P4
CNTRST
P4[6]
INT
P4
A0
P4
L
A0
P2
INT
P2
CNTRST
P2[6]
VSS
GND[5]
GND[5]
GND[5]
GND[5]
VSS
CNTRST
P3[6]
INT
P3
A0
P3
M
VDD1
A1
P2
A2
P2
CLK
P2
GND[5]
GND[5]
GND[5]
GND[5]
CLK
P3
A2
P3
A1
P3
VDD1
N
A3
P2
A4
P2
MKLD
P2
CNTLD
P2[6]
CNTLD
P3[6]
MKLD
P3[6]
A4
P3
A3
P3
P
VSS1
A5
P2
A6
P2
CNTINC
P2[6]
CNTINC
P3[6]
A6
P3
A5
P3
VSS1
R
A7
P2
A8
P2
A9
P2
CNTINT
P2[7]
CNTINT
P3[7]
A9
P3
A8
P3
A7
P3
T
A10
P2
A11
P2
MKRD
P2
CNTRD
P2[6]
CNTRD
P3[6]
MKRD
P3[6]
A11
P3
A10
P3
U
VSS1
A12
P2
A13
P2
OE
P2
VDD2
VSS2
VSS2
VDD2
VDD
VSS
VSS
VDD
VDD2
VSS2
VSS2
VDD2
OE
P3
A13
P3
A12
P3
VSS1
V
A14
P2[9]
A15
P2[8]
CE1
P2
CE0
P2
R/W
P2
I/O6
P2
VSS2
VSS2
I/O0
P2
NC
NC
I/O0
P3
VSS2
VSS2
I/O6
P3
R/W
P3
CE0
P3
CE1
P3
A15
P3[8]
A14
P3[9]
W
VDD1
UB
P2
I/O7
P1
I/O5
P1
I/O3
P1
I/O1
P1
I/O8
P2
I/O4
P2
I/O2
P2
MRST
CLKBIST
I/O2
P3
I/O4
P3
I/O8
P3
I/O1
P4
I/O3
P4
I/O5
P4
I/O7
P4
UB
P3
VDD1
Y
LB
P2
I/O8
P1
I/O6
P1
I/O4
P1
I/O2
P1
I/O0
P1
1/O7
P2
I/O5
P2
I/O3
P2
I/O1
P2
I/O1
P3
I/O3
P3
I/O5
P3
I/O7
P3
I/O0
P4
I/O2
P4
I/O4
P4
I/O6
P4
I/O8
P4
LB
P3
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