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CY7C1353B-40AC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1353B-40AC
Description  256Kx18 Flow-Through SRAM with NoBL Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1353B-40AC Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C1353B
PRELIMINARY
Document #: 38-05266 Rev. **
Page 7 of 15
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C to +150°C
Ambient Temperature with
Power Applied
.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND......... −0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[7]
.....................................−0.5V to V
DDQ + 0.5V
DC Input Voltage[7]
..................................−0.5V to V
DDQ + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature[8]
VDD/VDDQ
Com’l
0°C to
+70°C
3.3V
±5%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.465
V
VDDQ
I/O Supply Voltage
3.135
3.465
V
VOH
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
[9]
2.4
V
VOL
Output LOW Voltage
VDD = Min., IOL = 8.0 mA
[9]
0.4
V
VIH
Input HIGH Voltage
2.0
VDD +0.3V
V
VIL
Input LOW Voltage[7]
−0.3
0.8
V
IX
Input Load Current
GND
≤ V
I ≤ VDDQ
−5
5
mA
Input Current of MODE
−30
30
mA
IOZ
Output Leakage
Current
GND
≤ V
I ≤ VDDQ, Output Disabled
−5
5
mA
ICC
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz
375
mA
10-ns cycle, 100 MHz
350
mA
15-ns cycle, 66 MHz
250
mA
20-ns cycle, 50 MHz
200
mA
25-ns cycle, 40 MHz
175
mA
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz
90
mA
10-ns cycle, 100 MHz
80
mA
15-ns cycle, 66 MHz
60
mA
20-ns cycle, 50 MHz
40
mA
25-ns cycle, 40 MHz
30
mA
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
f = 0
All speed grades
5
mA
ISB3
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ − 0.3V
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz
80
mA
10-ns cycle, 100 MHz
70
mA
15-ns cycle, 66 MHz
50
mA
20-ns cycle, 50 MHz
40
mA
25-ns cycle, 40 MHz
30
mA
Notes:
7.
Minimum voltage equals
2.0V for pulse duration less than 20 ns.
8.
TA is the case temperature.
9.
The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads.


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