CY7C1370B
CY7C1372B
Document #: 38-05197 Rev. **
Page 5 of 27
Pin Definitions
Name
I/O Type
Description
A0
A1
A
Input-
Synchronous
Address inputs used to select one of the 524,288/1,048576 address locations.
Sampled at the rising edge of the CLK.
BWSa
BWSb
BWSc
BWSd
Input-
Synchronous
Byte Write Select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb
and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.
WE
Input-
Synchronous
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a Write sequence.
ADV/LD
Input-
Synchronous
Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order to load a new address.
CLK
Input-Clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
CE1
Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
CE2
Input-
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
Input-
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
Input-
Asynchronous
Output enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a Write sequence, during the first clock
when emerging from a deselected state and when the device has been deselected.
CEN
Input-
Synchronous
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when
required.
DQa
DQb
DQc
DQd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by AX during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state
condition. The outputs are automatically three-stated during the data portion of a Write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.DQ a, b, c and d are eight-bits wide.
DPa
DPb
DPc
DPd
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].
During Write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is
controlled by BWSc, and DPd is controlled by BWSd.DP a, b, c and d are one-bit wide
ZZ
Input-
Asynchronous
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
MODE
Input Pin
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
TDO
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA
only).
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