CY7C1370B
CY7C1372B
Document #: 38-05197 Rev. **
Page 7 of 27
Introduction
Functional Overview
The CY7C1370B/CY7C1372B are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the CEN input
signal. If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.8 ns (150-MHz
device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If the
CEN is active LOW and ADV/LD is asserted LOW, the address
presented to the device will be latched. The access can either
be a Read or Write operation, depending on the status of the
Write enable (WE). BWS[d:a] can be used to conduct byte
Write operations.
Write operations are qualified by the Write enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous CE1, CE2, CE3 and an asynchronous OE
simplify depth expansion. All operations (Reads, Writes, and
Deselects) are pipelined. ADV/LD should be driven LOW once
the device has been deselected in order to load a new address
for the next operation.
Single Read Accesses
A Read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a Read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.8 ns
(150-MHz device) provided OE is active LOW. After the first
clock of the Read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Burst Read Accesses
The CY7C1370B/CY7C1372B have on-chip burst counters
that allow the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to Ax is loaded into
the Address Register. The Write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DPa,b,c,d for CY7C1370B and DQa,b/DPa,b for
CY7C1372B). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided that the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DP
(DQa,b,c,d/DPa,b,c,d for CY7C1370B and DQa,b/DPa,b for
CY7C1372B) (or a subset for byte Write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the Write operation is controlled by
BWS
(BWSa,b,c,d
for
CY7C1370B
and
BWSa,b for
CY7C1372B) signals. The CY7C1370B/CY7C1372B provides
byte Write capability that is described in the Write Cycle
Description table. Asserting the Write enable input (WE) with
the selected Byte Write Select (BWS) input will selectively
write to only the desired bytes. Bytes not selected during a
byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify
Write operations. Byte Write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte Write operations.
Because the CY7C1370B/CY7C1372B is a common I/O
device, data should not be driven into the device while the
outputs are active. The OE can be deasserted HIGH before
presenting data to the DQ and DP (DQa,b,c,d/DPa,b,c,d for
CY7C1370B and DQa,b/DPa,b for CY7C1372B) inputs. Doing
so will three-state the output drivers. As a safety precaution,
DQ and
DP
(DQa,b,c,d/DPa,b,c,d for CY7C1370B and
DQa,b/DPa,b for CY7C1372B) are automatically three-stated
during the data portion of a Write cycle, regardless of the state
of OE.
Burst Write Accesses
The CY7C1370B/CY7C1372B has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BWS (BWSa,b,c,d for CY7C1370B and BWSa,b for
CY7C1372B) inputs must be driven in each cycle of the burst
Write in order to write the correct bytes of data.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
