CY7C1370B
CY7C1372B
Document #: 38-05197 Rev. **
Page 8 of 27
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation
Address
Used
CE
CEN
ADV/
LD/
WE
BWSX
CLK
Comments
Deselected
External
1
0
L
X
X
L–H
I/Os three-state following next
recognized clock.
Suspend
–
X1
X
X
X
L–H
Clock ignored, all operations
suspended.
Begin Read
External
0
0
0
1
X
L–H
Address latched.
Begin Write
External
0
0
0
0
Valid
L–H
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L–H
Burst Read operation. Previous
access was a Read operation.
Addresses incremented internally
in conjunction with the state of
Mode.
Burst Write
Operation
Internal
X
0
1
X
Valid
L–H
Burst Write operation. Previous
access was a Write operation.
Addresses incremented internally
in conjunction with the state of
MODE. Bytes written are deter-
mined by BWS[d:a].
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Notes:
1.
X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one byte Write Select is active;
BWSx = Valid signifies that the desired byte Write selects are asserted. See Write Cycle Description table for details.
2.
Write is defined by WE and BWSx. See Write Cycle Description table for details.
3.
The DQ and DP pins are controlled by the current cycle and the OE signal.
4.
CEN = 1 inserts wait states.
5.
Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6.
OE assumed LOW.
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