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CY7C1386B
CY7C1387B
Document #: 38-05195 Rev. **
Page 9 of 32
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter Description
Test
Conditions
Min. Max. Unit
IDDZZ
Sleep mode
standby
current
ZZ > VDD – 0.2V
20
mA
tZZS
Device
operation to
ZZ
ZZ > VDD – 0.2V
2tCYC ns
tZZREC
ZZ recovery
time
ZZ < 0.2V
2tCYC
ns
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