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CY7C1381B
CY7C1383B
Document #: 38-05196 Rev. **
Page 7 of 31
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port (TAP) state machine. Sampled on the
rising edge of TCK (BGA only).
TCK
JTAG Serial Clock
Serial clock to the JTAG circuit (BGA only).
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V
–5% +10% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the
system.
VDDQ
I/O Power Supply
Power supply for the I/O circuitry.
VSSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
NC
–
No connects. Pins are not internally connected.
32M
64M
128M
–
No connects. Reserved for address expansion. Pins are not internally
connected.
Pin Definitions (continued)
Name
I/O
Description
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