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CY7C4801/4811/4821
CY7C4831/4841/4851
Document #: 38-06005 Rev. **
Page 6 of 23
Switching Characteristics Over the Operating Range
7C48X1-10
7C48X1-15
7C48X1-25
7C48X1-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
100
66.7
40
28.6
MHz
tA
Data Access Time
2
8
2
10
2
15
2
20
ns
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
3.5
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set-Up Time
3.5
4
6
7
ns
tENH
Enable Hold Time
0.5
1
1
2
ns
tRS
Reset Pulse Width[8]
10
15
25
35
ns
tRSS
Reset Set-Up Time
8
10
15
20
ns
tRSR
Reset Recovery Time
8
10
15
20
ns
tRSF
Reset to Flag and Output Time
10
15
25
35
ns
tOLZ
Output Enable to Output in Low Z[9]
0
0
0
0
ns
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[9]
3
7
3
8
3
12
3
15
ns
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tSKEW1
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag
15
15
18
20
ns
Notes:
8.
Pulse widths less than minimum values are not allowed.
9.
Values guaranteed by design, not currently tested.
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