CY7C4425/4205/4215
CY7C4225/4235/4245
6
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tPAEasynch
Clock to Programmable Almost-Empty Flag[12]
(Asynchronous mode, VCC/SMODE tied to VCC)
12
16
20
25
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tHF
Clock to Half-Full Flag
12
16
20
25
ns
tXO
Clock to Expansion Out
7
10
15
20
ns
tXI
Expansion in Pulse Width
3
6.5
10
14
ns
tXIS
Expansion in Set-Up Time
4.5
5
10
15
ns
tSKEW1
Skew Time between Read Clock and Write
Clock for Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write
Clock for Empty Flag
5
6
10
12
ns
tSKEW3
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Pro-
grammable Almost Full Flags.
10
15
18
20
ns
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Switching Waveforms
Notes:
10. Pulse widths less than minimum values are not allowed.
11.
Values guaranteed by design, not currently tested.
12. PAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
13. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Write Cycle Timing
tCLKH
tCLKL
NO OPERATION
tDS
tSKEW1
tENS
WEN
tCLK
tDH
tWFF
tWFF
tENH
WCLK
D0 –D17
FF
REN
RCLK
42X5–6
[13]
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