DS1077L

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Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain high.

Start data transfer: A change in the state of the data line from high to low while the clock is high

defines a START condition.

Stop data transfer: A change in the state of the data line from low to high while the clock line is high

defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line is

stable for the duration of the HIGH period of the clock signal. The data on the line must be changed

during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited, and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a

ninth bit.

Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)

are defined. The DS1077L works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse which is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into account. When the DS1077L EEPROM is being written

to, it will not be able to perform additional responses. In this case, the slave DS1077L will send a ‘not

acknowledge’ to any data transfer request made by the master. It will resume normal operation when the

EEPROM operation is complete.

A master must signal an end-of-data to the slave by not generating an acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the

master to generate the STOP condition.

DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 2

MSB

slave address

R/W

direction

bit

SDA

SCL

START

CONDITION

12

678

9

12

8

9

STOP CONDITION

OR

REPEATED

START CONDITION

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acknowledgement

signal from receiver

acknowledgement

signal from receiver

ACK

ACK

repeated if more bytes

are transferred