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AX88780 Datasheet(PDF) 9 Page - ASIX Electronics Corporation |
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AX88780 Datasheet(HTML) 9 Page - ASIX Electronics Corporation |
9 / 49 page AX88780 HD17 IO3, 8mA 126 Data bus bit17, internal pull low. HD18 IO3, 8mA 125 Data bus bit18, internal pull low. HD19 IO3, 8mA 124 Data bus bit19, internal pull low. HD20 IO3, 8mA 122 Data bus bit20, internal pull low. HD21 IO3, 8mA 121 Data bus bit21, internal pull low. HD22 IO3, 8mA 120 Data bus bit22, internal pull low. HD23 IO3, 8mA 118 Data bus bit23, internal pull low. HD24 IO3, 8mA 116 Data bus bit24, internal pull low. HD25 IO3, 8mA 114 Data bus bit25, internal pull low. HD26 IO3, 8mA 113 Data bus bit26, internal pull low. HD27 IO3, 8mA 112 Data bus bit27, internal pull low. HD28 IO3, 8mA 111 Data bus bit28, internal pull low. HD29 IO3, 8m 110 Data bus bit29, internal pull low. HD30 IO3, 8mA 109 Data bus bit30, internal pull low. HD31 IO3, 8mA 108 Data bus bit31, internal pull low. HA1 I3 42 Address bus bit1. HA2 I3 41 Address bus bit2. HA3 I3 34 Address bus bit3. HA4 I3 33 Address bus bit4. HA5 I3 32 Address bus bit5. HA6 I3 31 Address bus bit6. HA7 I3 30 Address bus bit7. HA8 I3 29 Address bus bit8. HA9 I3 28 Address bus bit9. HA10 I3 26 Address bus bit10. HA11 I3 25 Address bus bit11. HA12 I3 24 Address bus bit12. HA13 I3 23 Address bus bit13. HA14 I3 22 Address bus bit14. HA15 I3 21 Address bus bit15. WEN I3 44 Data Write Enable: WEN is driven by Host site, and it is active low. CSN I3 45 Chip Select Enable. CSN is driven by host site. It is active low. OEN I3 43 Data Output Enable: OEN is driven by the host site, and it is active low. 2.3 EEPROM Interface (Optional) Table 2 : EEPROM Interface signals group Pin Name Type Pin No. Pin Description EECLK O3, 12mA 47 A low speed clock to EEPROM EECS O3, 12mA 48 Chip select to EEPROM device. This pin will be treated as full-duplex indicator when bit10 of PHY_CTRL register is set to high. It is active high in full-duplex mode, and low in half-duplex mode. EEDI O3, 12mA 49 Data to EEPROM, valid in EECS is high and EECLK in rising edge. This pin will be treated as collision indicator when bit10 of PHY_CTRL register is set to high. It is active high in collision indicator. EEDO I3, PD 50 Data from EEPROM 9 ASIX ELECTRONICS CORPORATION |
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