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74ALVT16899 Datasheet(PDF) 2 Page - NXP Semiconductors |
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74ALVT16899 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 20 page Philips Semiconductors Product specification 74ALVT16899 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 2 1998 Jun 30 853-2090-19651 FEATURES • Symmetrical (A and B bus functions are identical) • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions • Independent transparent latches for A-to-B and B-to-A directions • Selectable ODD/EVEN parity • Continuously checks parity of both A bus and B bus latches as ERRA and ERRB • Open-collector ERR output • Ability to simultaneously generate and check parity • Can simultaneously read/latch A and B bus data • Output capability: +64 mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model • Power up 3-State • Power-up reset • No bus current loading when output is tied to 5 V bus • Live insertion/extraction permitted • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs DESCRIPTION The 74ALVT16899 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. The 74ALVT16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. The 74ALVT16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. FUNCTIONAL DESCRIPTION: The 74ALVT16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of: • Transparent latch / 1 bus latched / both buses latched • Feed-through parity / generate parity • Check in bus parity / check out bus parity / check in and out bus parity QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYPICAL UNIT SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V 2.5 V 3.3 V UNIT tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF 2.0 2.2 1.5 1.7 ns tPLH tPHL Propagation delay An to ERRA CL = 50pF 9.8 7.0 7.8 5.1 ns CIN Input capacitance VI = 0V or VCC 3 3 pF CI/O Output capacitance Outputs disabled; VO = 0V or VCC 9 9 pF ICCZ Quiescent supply current Outputs disabled 40 70 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40 °C to +85°C 74ALVT16899 AV16899 DL SOT371-1 56-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVT16899 DGG AV16899 DGG SOT364-1 |
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