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IDT72V73273 Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72V73273 Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 37 page 7 INDUSTRIAL TEMPERATURERANGE IDT72V73273 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS MICROPROCESSOR INTERFACE The IDT72V73273’s microprocessor interface looks like a standard RAM interface to improve integration into a system. With a 16-bit address bus and a16-bitdatabusallmemoriescanbeaccessed. UsingtheTSImicroprocessor interface, reads and writes are mapped into Data and Connection memories. By allowing the internal memories to be randomly accessed, the controlling microprocessor has more time to manage other peripheral devices andcanmoreeasilyandquicklygatherinformationandsetuptheswitchpaths. Table 1 shows the mapping of the addresses into internal memory blocks. In ordertominimizetheamountofmemorymappedspacehowever,theMemory Select(MS1-0)bitsintheControlRegistermustbewrittentofirsttoselectbetween theConnectionMemoryHIGH,theConnectionMemoryLOW,orDataMemory. Effectively,theMemorySelectbitsactasaninternalmuxtoselectbetweenthe Data Memory, Connection Memory HIGH, and Connection Memory LOW. MEMORY MAPPING Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters and memoriesoftheIDT72V73273.Themostsignificantbitoftheaddressselect between the registers and internal memories. See Table 1 for mappings. Asexplainedintheinitializationsections,aftersystempower-up,theTDRSR and RDRSR, should be programmed immediately to establish the desired switchingconfiguration. The data in the Control Register consists of the Software Reset, RX/TX Bypass, Output Enable Polarity, All Output Enable, Full Block Programming, BlockProgrammingData,BeginBlockProgrammingEnable,ResetConnection Memory LOW in Block Programming, Output Standby, and Memory Select. SOFTWARE RESET The Software Reset serves the same function as the hardware reset. As with the hard reset, the Software Reset must also be set HIGH for 20ns before bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware Reset is LOW, internal registers and other memories may be read or written. During Software Reset, the microprocessor port is still able to read from all internal memories. The only write operation allowed during a Software Reset istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset. CONNECTION MEMORY CONTROL If the ODE pin and the Output Standby bit are LOW, all output channels will be in three-state. See Table 2 for detail. If MOD2-0 of the Connection Memory HIGH is 1-0-0 accordingly, the output channel will be in Processor Mode. In this case the lower eight bits of the Connection Memory LOW are output each frame until the MOD2-0 bits are changed. If MOD2-0 of the Connection Memory HIGH are 0-0-1 accordingly, the channel will be in Constant Delay Mode and bits 14-0 are used to address a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are 0-0-0, the channel will be in Variable Delay Mode and bits 14-0 are used to addressalocationinDataMemory.IfMOD2-0oftheConnectionMemoryHIGH are 1-1-1, the channel will be in High-Impedance mode and that channel will be in three-state. RX/TX INTERNAL BYPASS When the Bypass bit of control registers is 1, all RX streams will be “shorted” toTX ineffectbypassingallinternalcircuitryoftheTSI. Thiseffectivelysetsthe TSItoa1-to-1switchmodewithminimalI/Odelay. Azerocanbewrittentoallow normaloperation.TheintentionofthismodeistominimizethedelayfromtheRX input to the TX output making the TSI “invisible”. INITIALIZATION OF THE IDT72V73273 Afterpowerup,thestateoftheConnectionMemoryisunknown. Assuch,the outputs should be put in High-Impedance by holding the ODE pin LOW. While theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock Programmingfeatureandprogramtheactivepathsviathemicroprocessorbus. Once the device is configured, the ODE pin (or Output Standby bit depending on initialization) can be switched to enable the TSI switch. |
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