1

Rev. C

07/25/05

IS61LV2568L

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

JULY 2005

FEATURES

• High-speed access time: 8, 10 ns

• Operating Current: 50mA (typ.)

• Standby Current: 700µA (typ.)

• Multiple center power and ground pins for

greater noise immunity

• Easy memory expansion with

CE and OE

options

•

CE power-down

• TTL compatible inputs and outputs

• Single 3.3V power supply

• Packages available:

– 36-pin 400-mil SOJ

– 44-pin TSOP (Type II)

• Lead-free available

DESCRIPTION

The

262,144-word by 8-bit CMOS static RAM. The IS61LV2568L

is fabricated using

nology. This highly reliable process coupled with innova-

tive circuit design techniques, yields higher performance

and low power consumption devices.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down to 36mW (max.) with CMOS input levels.

The IS61LV2568L operates from a single 3.3V power

supply and all inputs are TTL-compatible.

The IS61LV2568L is available in 36-pin 400-mil SOJ and

44-pin TSOP (Type II) packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A17

CE

OE

WE

256K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

256K x 8 HIGH-SPEED CMOS STATIC RAM