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LM2717MT-ADJ Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LM2717MT-ADJ Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 16 page Electrical Characteristics (Continued) Specifications in standard type face are for T J = 25˚C and those with boldface type apply over the full Operating Tempera- ture Range (T J = −40˚C to +125˚C). VIN = 5V, IL = 0A, and FSW = 300kHz unless otherwise specified. Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units F SW Switching Frequency R F = 46.4k 240 300 360 kHz R F = 22.6k 480 600 720 kHz I SHDN1 Buck 1 Shutdown Pin Current 0V < V SHDN1 < 7.5V −5 5 µA I SHDN2 Buck 2 Shutdown Pin Current 0V < V SHDN2 < 7.5V −5 5 µA I L1 Buck 1 Switch Leakage Current V IN = 20V 0.01 5 µA I L2 Buck 2 Switch Leakage Current V IN = 20V 0.01 5 µA R DSON1 Buck 1 Switch R DSON (Note 9) I SW = 100mA 160 180 300 m Ω R DSON2 Buck 2 Switch R DSON (Note 9) I SW = 100mA 160 180 300 m Ω Th SHDN1 Buck 1 SHDN Threshold Output High 1.8 1.36 V Output Low 1.33 0.7 Th SHDN2 Buck 2 SHDN Threshold Output High 1.8 1.36 V Output Low 1.33 0.7 I SS1 Buck 1 Soft Start Pin Current 4 9 15 µA I SS2 Buck 2 Soft Start Pin Current 4 9 15 µA UVP On Threshold 4 3.8 V Off Threshold 3.6 3.3 θ JA Thermal Resistance (Note 10) TSSOP, package only 115 ˚C/W Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance. The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) −TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k Ω resistor into each pin. Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 5: Typical numbers are at 25˚C and represent the most likely norm. Note 6: Duty cycle affects current limit due to ramp generator. Note 7: Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. Input Voltage. Note 8: Bias current flows into FB pin. Note 9: Includes the bond wires and package leads, RDSON from VIN pin(s) to SW pin. Note 10: Refer to National’s packaging website for more detailed thermal information and mounting techniques for the TSSOP package. www.national.com 6 |
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