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74AVC16374 Datasheet(PDF) 10 Page - NXP Semiconductors |
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74AVC16374 Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 2000 Mar 09 10 Philips Semiconductors Product Specification 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state 74AVC16374 AC WAVEFORMS handbook, full pagewidth MNA579 nCP input nQn output tPHL tPLH tW VM VOH VI GND VOL VM VM 1/fmax Fig.7 Clock input (nCP) to output (nQn) propagation delays. VCC VM VI ≤2.3 to 2.7 V 0.5 × VCC VCC 3.0 to 3.6 V 0.5 × VCC VCC VOL and VOH are typical output voltage drop that occur with the output load. handbook, full pagewidth MNA478 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM Fig.8 3-state enable and disable times. VCC VM VX VY VI ≤2.3 to 2.7 V 0.5 × VCC VOL + 0.15 V VOH − 0.15 V VCC 3.0 to 3.6 V 0.5 × VCC VOL + 0.3 V VOH − 0.3 V VCC VOL and VOH are typical output voltage drop that occur with the output load. |
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