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74AVC16834 Datasheet(PDF) 2 Page - NXP Semiconductors |
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74AVC16834 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 10 page  Philips Semiconductors Preliminary specification 74AVC16834 18-bit registered driver with inverted register enable (3-State) 2 1999 Jul 23 FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A/5/7. • CMOS low power consumption • Input/output tolerant up to 3.6 V • DCO (Dynamic Controlled Output) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation • Low inductance multiple V CC and GND pins for minimum noise and ground bounce • Power off disables 74AVC16834 outputs, permitting Live Insertion DESCRIPTION The 74AVC16834 is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See the graphs on page 8 for typical curves. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 NC NC Y0 Y1 Y2 Y3 Y4 Y5 GND VCC GND Y6 Y7 Y8 Y9 Y10 Y11 GND Y12 Y13 Y14 VCC Y15 Y16 GND Y17 OE LE GND NC A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 CP GND SH00156 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.0 ns; CL = 30 pF. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay An to Yn VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V 2.6 2.0 1.7 ns tPHL/tPLH Propagation delay LE to Yn; CP to Yn VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V 2.9 2.3 1.9 ns CI Input capacitance 5.0 pF CPD Power dissipation capacitance per buffer VI = GND to VCC1 Outputs enabled 25 pF CPD Power dissi ation ca acitance er buffer VI = GND to VCC1 Output disabled 6 F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40 °C to +85°C 74AVC16834 DGG SOT364-1 |
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