IC41C82052S

IC41LV82052S

8

Integrated Circuit Solution Inc.

DR016-0A 06/12/2001

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device

in a monotonic manner.

6. Measured with a load equivalent to one TTL gate and 50 p..

9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the

the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back

15. Output parameter (I/O) is referenced to corresponding CAS input.

16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a

LATE WRITE or READ-MODI.Y-WRITE is not possible.

17. Write command is defined as WE going low.

that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW

20. Determined by falling edge of CAS.

21. Determined by rising edge of CAS.

22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-

MODI.Y-WRITE cycles.

23. CAS must meet minimum pulse width.

24. The 3 ns minimum is a parameter guaranteed by design.

25. Enables on-chip refresh and address counters.