.EATURES

• .AST Page Mode access cycle

• TTL compatible inputs and outputs

• Refresh Interval:

Refresh Mode: 4)5-Only,

+)5-before-4)5 (CBR), and Hidden,

2,048 cycles/32 ms

Self refresh Mode 2,048 cycles/128 ms

• JEDEC standard pinout

• Single power supply:

5V±10% or 3.3V ± 10%

• Byte Write and Byte Read operation via

+)5

DESCRIPTION

The

mance CMOS Dynamic Random Access Memory. The .ast

Page Mode allows 2,048 random accesses within a single row

with access cycle time as short as 20 ns per 8-bit word.

These features make the 82052S Series ideally suited for high-

bandwidth graphics, digital signal processing, high-performance

computing systems, and peripheral applications.

The 82052S Series is packaged in a 28-pin 300mil SOJ and a

28 pin TSOP-2

IC41C82052S

IC41LV82052S

2M x 8 (16-MBIT) DYNAMIC

RAM

WITH .AST PAGE MODE

Integrated Circuit Solution Inc.

1

DR016-0A 06/12/2001

KEY TIMING PARAMETERS

Parameter

-50

-60 Unit

60

ns

15

ns

30

ns

25

ns

84

104

ns

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

PRODUCT SERIES OVERVIEW

Part No.

Refresh

Voltage

IC41C82052S

2K

5V ± 10%

IC41LV82052S

2K

3.3V ± 10%

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

I/O0

I/O1

I/O2

I/O3

WE

RAS

NC

A10

A0

A1

A2

A3

VCC

GND

I/O7

I/O6

I/O5

I/O4

CAS

OE

A9

A8

A7

A6

A5

A4

GND

PIN DESCRIPTIONS

A0-A10

Address Inputs

I/O0-7

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

CAS

Column Address Strobe

Vcc

Power

GND

Ground

NC

No Connection

PIN CON.IGURATION

28 Pin SOJ, TSOP-2