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IC41SV4105-70TG Datasheet(PDF) 8 Page - Integrated Circuit Solution Inc |
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IC41SV4105-70TG Datasheet(HTML) 8 Page - Integrated Circuit Solution Inc |
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8 / 17 page  IC41SV4105 8 Integrated Circuit Solution Inc. DR032-0A 10/29/2001 AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 - 70 - 100 Symbol Parameter Min. Max. Min. Max. Min. Max. Units tACH Column-Address Setup Time to CAS 15 − 15 − 15 − ns Precharge during WRITE Cycle tOEH OE Hold Time from WE during 10 − 20 − 25 − ns READ-MODIFY-WRITE cycle(18) tDS Data-In Setup Time(15, 22) 0 − 0 − 0 − ns tDH Data-In Hold Time(15, 22) 8 − 15 − 20 − ns tRWC READ-MODIFY-WRITE Cycle Time 125 − 185 − 240 − ns tRWD RAS to WE Delay Time during 70 − 100 − 130 − ns READ-MODIFY-WRITE Cycle(14) tCWD CAS to WE Delay Time(14, 20) 34 − 45 − 55 − ns tAWD Column-Address to WE Delay Time(14) 42 − 60 − 85 − ns tPC Fast Page Mode READ or WRITE 20 − 45 − 60 − ns Cycle Time tRASP Fast Page Mode RAS Pulse Width 50 100K 70 100K 100 100K ns tCPA Access Time from CAS Precharge(15) -27 - 40 - 55 ns tPRWC Fast Page Mode READ WRITE 47 − 100 − 120 − ns Cycle Time tOFF Output Buffer Turn-Off Delay from 3 15 3 15 3 15 ns CAS or RAS(13,15,19, 24) tCSR CAS Setup Time (CBR REFRESH)(20, 25) 5 − 5 − 5 − ns tCHR CAS Hold Time (CBR REFRESH)( 21, 25) 10 − 10 − 10 − ns tORD OE Setup Time prior to RAS during 0 − 0 − 0 − ns HIDDEN REFRESH Cycle tREF Auto Refresh Period 1,024 Cycles − 16 − 16 − 16 ms tT Transition Time (Rise or Fall)(2, 3) 350 3 50 3 50 ns AC TEST CONDITIONS Output load: One TTL Load and 100 pF Input timing reference levels: VIH = 1.4V, VIL = 0.6V Output timing reference levels: VOH = 1.4V, VOL = 0.6V |
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