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IC42S16102-6TIG Datasheet(PDF) 11 Page - Integrated Circuit Solution Inc |
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IC42S16102-6TIG Datasheet(HTML) 11 Page - Integrated Circuit Solution Inc |
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11 / 78 page  IC42S16102 Integrated Circuit Solution Inc. 11 DR042-0A 01/18/2005 Mode Register Set Command (CS, RAS, CAS, WE = LOW) The IC42S16102 product incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulated power-on sequence should be executed and then the IC42S16102 should be initialized by executing a mode register set command. Note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated). Another command cannot be executed after a mode register set command until after the passage of the period tMCD, which is the period required for mode register set command execution. Active Command (CS, RAS = LOW, CAS, WE= HIGH) The IC42S16102 includes two banks of 4096 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs. Precharge Command (CS, RAS, WE = LOW, CAS = HIGH) This command starts precharging the bank selected by pins A10 and A11. When A10 is HIGH, both banks are precharged at the same time. When A10 is LOW, the bank selected by A11 is precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period tRP, which is the period required for bank precharging. This command corresponds to the RAS signal from LOW to HIGH in conventional DRAMs Read Command (CS, CAS = LOW, RAS, WE = HIGH) This command selects the bank specified by the A11 pin and starts a burst read operation at the start address specified by pins A0 to A9. Data is output following CAS latency. The selected bank must be activated before executing this command. When the A10 pin is HIGH, this command functions as a read with auto-precharge command. After the burst read completes, the bank selected by pin A11 is precharged. When the A10 pin is LOW, the bank selected by the A11 pin remains in the activated state after the burst read completes. Write Command (CS, CAS, WE = LOW, RAS = HIGH) When burst write mode has been selected with the mode register set command, this command selects the bank specified by the A11 pin and starts a burst write operation at the start address specified by pins A0 to A9. This first data must be input to the I/O pins in the cycle in which this command. The selected bank must be activated before executing this command. When A10 pin is HIGH, this command functions as a write with auto-precharge command. After the burst write completes, the bank selected by pin A11 is precharged. When the A10 pin is low, the bank selected by the A11 pin remains in the activated state after the burst write completes. After the input of the last burst write data, the application must wait for the write recovery period (tDPL, tDAL) to elapse according to CAS latency. Auto-Refresh Command (CS, RAS, CAS = LOW, WE, CKE = HIGH) This command executes the auto-refresh operation. The row address and bank to be refreshed are automatically generated during this operation. Both banks must be placed in the idle state before executing this command. The stipulated period (tRC) is required for a single refresh operation, and no other commands can be executed during this period. The device goes to the idle state after the internal refresh operation completes. This command must be executed at least 4096 times every 64 ms. This command corresponds to CBR auto-refresh in conventional DRAMs. |
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