IC42S32800-7TIG datasheet(6/62 Pages) ICSI

Part #	IC42S32800-7TIG

Description	2M x 32 Bit x 4 Banks (256-MBIT) SDRAM

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Manufacturer	ICSI [Integrated Circuit Solution Inc]

Direct Link	http://www.icsi.com.tw

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IC42S32800

IC42S32800L

6

Integrated Circuit Solution Inc.

DR046-0B 12/21/2004

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth

table for the operation commands.

Table 2.Truth Table (Note (1),(2))

Note:

1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high

2. CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BS signal.

4. Device state is 1,2,4,8,and full page burst operation.

5. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle,device state is clock suspend mode.

6. DQM0-3

Command

State

CKEn-1 CKE

DQM(6) BS0,1

A10 A11,A9-0

CS# RAS# CAS# WE#

BankActivate

Idle (3)

H

X

V

Row address

L

H

BankPrecharge

Any

H

X

V

L

X

L

H

L

PrechargeAll

Any

H

X

H

X

L

H

L

Write

Active (3)

HX

X

V

L

H

L

Write and Auto Precharge Active (3)

HX

X

V

H

L

H

L

Read

Active (3)

HX

X

V

L

H

L

H

Read and Autoprecharge

Active (3)

HX

X

V

H

L

H

L

H

Mode Register

Set Idle

H

X

OP code

L

No-Operation

Any

H

X

L

H

Burst Stop

Active(4)

HX

X

L

H

L

Device Deselect

Any

H

X

H

X

AutoRefresh

Idle

H

X

L

H

SelfRefresh Entry

Idle

H

L

X

L

H

SelfRefresh Exit

Idle

L

H

X

H

X

(SelfRefresh)

L

H

Clock Suspend Mode Entry Active

H

L

X

Power Down Mode Entry

Any(5)

HL

X

H

X

LH

H

Clock Suspend Mode Exit Active

L

H

X

Power Down Mode Exit

Any

L

H

X

H

X

(PowerDown)

L

H

Data Write/Output Enable Active

H

X

L

X

Data Mask/Output Disable Active

H

X

H

X

Column

address

(A0 ~A7)

Column

address

(A0 ~A7)

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