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IC42S32202-8BI Datasheet(PDF) 4 Page - Integrated Circuit Solution Inc |
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IC42S32202-8BI Datasheet(HTML) 4 Page - Integrated Circuit Solution Inc |
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4 / 62 page  IC42S32202/L 4 Integrated Circuit Solution Inc. DR042-0C 08/17/2004 PIN DESCRIPTIONS Table 1.Pin Details of IC42S32202 and IC42S32202L Symbol Type Description CLK Input Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn- chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low.When all banks are in the idle state,deactivating the clock controls the entry to the Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode. The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing low standby power. BS0,BS1 Input Bank Select:BS0 and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge command is being applied. A0-A10 Input Address Inputs:A0-A10 are sampled during the BankActivate command (row address A0-A10)and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 256K available in the respective bank.During a Precharge command,A10 is sampled to determine if all banks are to be precharged (A10 =HIGH). The address inputs also provide the op-code during a Mode Register Set . CS# Input Chip Select:CS#enables (sampled LOW)and disables (sampled HIGH)the command decoder.All commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on systems with multiple banks.It is considered part of the command code. RAS# Input Row Address Strobe:The RAS#signal defines the operation commands in conjunction with the CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are as- serted “LOW”and CAS#is asserted “HIGH,”either the BankActivate command or the Precharge command is selected by the WE#signal.When the WE#is asserted “HIGH,”the BankActivate com- mand is selected and the bank designated by BS is turned on to the active state.When the WE#is asserted “LOW,”the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. CAS# Input Column Address Strobe:The CAS#signal defines the operation commands in conjunction with the RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held “HIGH”and CS#is asserted “LOW,”the column access is started by asserting CAS#”LOW.”Then,the Read or Write command is selected by asserting WE# “LOW”or “HIGH.” WE# Input Write Enable:The WE#signal defines the operation commands in conjunction with the RAS#and CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the BankActivate or Precharge command and Read or Write command. DQM0-3 Input Data Input/Output Mask:DQM0-DQM3 are byte specific,nonpersistent I/O buffer controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1 masks DQ15-DQ8,and DQM0 masks DQ7-DQ0. DQ0-31 Input/Output Data I/O:The DQ0-31 input and output data are synchronized with the positive edges of CLK.The I/Os are byte-maskable during Reads and Writes. |
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