2

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832

IC61SP12836

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• 100-Pin TQFP (JEDEC LQFP) and

119-pin PBGA package

• Single +3.3V, +10%, –5% power supply

• Power-down snooze mode

DESCRIPTION

The

power synchronous static RAM designed to provide a burstable,

high-performance, secondary cache for the Pentium™, 680X0™,

and PowerPC™ microprocessors. It is organized as 131,072

words by 32 bits, fabricated with

technology. The device integrates a 2-bit burst counter, high-

speed SRAM core, and high-drive capability outputs into a

single monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single clock

input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,

BW4 controls DQd, conditioned by BWE being LOW. A LOW

on

GW input would cause all bytes to be written.

Bursts can be initiated with either

ADSP (Address Status

Processor) or

ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated internally

by the IC61SP12832,IC61SP12836 and controlled by the

ADV

(burst address advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

128K x 32, 128K x 36 SYNCHRONOUS

PIPELINED STATIC RAM

FAST ACCESS TIME

Symbol

Parameter

-166

-150

-133

-117

-5

Units

Clock Access Time

3.5

3.8

4

4

5

ns

Cycle Time

6

6.7

7.5

8.5

10

ns

Frenquency

166

150

133

117

100

MHz