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IC61SF25632D-9.5TQ Datasheet(PDF) 2 Page - Integrated Circuit Solution Inc |
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IC61SF25632D-9.5TQ Datasheet(HTML) 2 Page - Integrated Circuit Solution Inc |
2 / 19 page IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D 2 Integrated Circuit Solution Inc. SSR020-0A 9/03/2002 ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. FEATURES • Flowthrough Mode operation. • User-selectable Output Drive Strength with XQ Mode. • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +3.3V, +10%, –5% core power supply • Power-down snooze mode • 2.5V or 3.3V I/O Supply • Snooze MODE for reduced-power standby • T version (three chip selects) • D version (two chip selects) 256K x 32, 256K x 36, 512K x 18 8Mb SYNCBURST Flow throughSRAMs DESCRIPTION ICSI's 8Mb SyncBurst Flowthrough SRAMs integrate a 512k x 18, 256k x 32, or 256k x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Applications Applications Applications Applications Applications The ICSI SyncBurst Flowthrough SRAM family employs high- speed ,low-power CMOS designs that are fabricated using an advanced CMOS process to provide Level 2 Cache applica- tions supporting Pentium and PowerPC microprocessors originally, the device now finds application ranging from DSP main store to networking chip set support. Controls All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst ad- dresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. Byte Write and Global Write Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable ( BWE).input combined with one or more individualbyte write signals ( BWx). In addition, Global Write ( GW) is available for writing all bytes at one time, regardless of the byte write controls. IOL/IOH Drive strength Options The XQ pin allows selection between high drive strength (XQ low) for multi-drop bus applications and normal drive strength (XQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Snooze Mode Low power (Snooze mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Snooze mode. FAST ACCESS TIME Symbol -6.5 -7.5 -8.5 -9.5 Units Flow tKQ 6.5 7.5 8.5 9.5 ns Through tKC 7.5 8.5 10 11 ns 2-1-1-1 ICC1 270 260 240 230 mA |
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