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IC61SF25636D-6.5BI Datasheet(PDF) 9 Page - Integrated Circuit Solution Inc |
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IC61SF25636D-6.5BI Datasheet(HTML) 9 Page - Integrated Circuit Solution Inc |
9 / 19 page IC61SF25632T/D IC61SF25636T/D IC61SF51218T/D Integrated Circuit Solution Inc. 9 SSR020-0A 9/03/2002 PIN CONFIGURATION PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A2-A18 Synchronous Address Inputs CLK Synchronous Clock ADSP Synchronous Processor Address Status ADSC Synchronous Controller Address Status ADV Synchronous Burst Address Advance BWa -BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable GW Synchronous Global Write Enable CE,CE2,CE2 Synchronous Chip Enable OE Output Enable DQa-DQb Synchronous Data Input/Output MODE Burst Sequence Mode Selection XQ Output Drive Control VCC +3.3V Power Supply GND Ground VCCQ Isolated Output Buffer Supply : +3.3V or 2.5V ZZ Snooze Enable DQPa-DQPb Parity Data I/O DQPa is parity for DQa1-8;DQPb is parity for DQb1-8 512K x18 SA NC NC VCCQ GND NC DQPa DQa8 DQa7 GND VCCQ DQa6 DQa5 GND NC VCC ZZ DQa4 DQa3 VCCQ GND DQa2 DQa1 NC NC GND VCCQ NC NC NC NC NC NC VCCQ GND NC NC DQb1 DQb2 GND VCCQ DQb3 DQb4 GND/NC VCC XQ GND DQb5 DQb6 VCCQ GND DQb7 DQb8 DQPb NC GND VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100-Pin TQFP (T Version) Note:Pin 14 no connection is acceptable |
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