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IS24C32A-2GLI Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS24C32A-2GLI Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
2 / 17 page 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/12/06 IS24C32A/B IS24C64A/B ISSI® > CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR WORD ADDRESS COUNTER HIGH VOLTAGE GENERATOR, TIMING & CONTROL EEPROM ARRAY Y DECODER DATA REGISTER Clock DI/O ACK 8 5 6 7 4 GND WP SCL SDA Vcc nMOS 1 2 3 A2 A1 A0 PIN DESCRIPTIONS A0-A2 Address Inputs SDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GND Ground SCL This input clock pin is used to synchronize the data transfer to and from the device. SDA The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc. A0, A1, A2 The A0, A1 and A2 are the device address inputs that are hardwired or left not connected for hardware compatibility with the 24C16. When pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system. When the pins are not hardwired, the default values of A0, A1, and A2 are zero. PIN CONFIGURATION 8-Pin DIP, SOIC, TSSOP, and MSOP 1 2 3 4 8 7 6 5 A0 A1 A2 GND VCC WP SCL SDA FUNCTIONAL BLOCK DIAGRAM WP WP is the Write Protect pin. The input level determines if all, partial, or none of the array is protected from modifications. Write Protection Array Addresses Protected WP IS24C32A/64A IS24C32B IS24C64B GND or floating None None None Vcc Entire Array C00h 1800h -FFFh -1FFFh |
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