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IS25C256-3GLA3 Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS25C256-3GLA3 Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
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4 / 17 page  4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Advanced Information Rev. 00E 06/13/06 IS25C128 IS25C256 ISSI® STATUS REGISTER Table 1. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 WPEN X X X BP1 BP0 WEN RDY The status register contains 8-bits for write protection control and write status. (See Table 1). It is the only region of memory other than the main array that is accessible by the user. The Status Register is Read-Only if either: a) Hardware Write Protection is enabled or b) WEN is set to 0. If neither is true, it can be modified by a valid instruction. Ready ( RDY RDY RDY RDY RDY), Bit 0: When RDY = 1, it indicates that the device is busy with a write cycle. RDY = 0 indi- cates that the device is ready for an instruction. If RDY = 1, the only command that will be handled by the device is Read Status Register. Don’t Care, Bits 4-6: Each of these bits can receive either 0 or 1, but values will not be retained. When these bits are read from the register, they are always 0. Write Protect Enable (WPEN), Bit 7: This bit can be used in conjunction with WP pin to enable Hardware Write Protection, which causes the Status Register to be read-only. The memory array is not protected by this mode. Hardware Write Protection requires that WP = 0 and WPEN = 1; it is disabled otherwise. Note: WPEN cannot be changed from 1 to 0 if the WP pin is already set to Low. (See Table 4 for data protection relationship) Notes: 1. X = Don't care bit. 2. During internal write cycles, bits 0 to 7 are temporarily 1's. Block Protect (BP1, BP0), Bits 2-3: Together, these bits represent one of four block protection configurations implemented for the memory array. (See Table 2 for details.) BP0 and BP1 are non-volatile cells similar to regular array cells, and factory programmed to 0. The block of memory defined by these bits is always protected, regardless of the setting of WPEN, WP , or WEN. Table 2. Block Protection Status Register Bits Array Addresses Protected Level BP1 BP0 IS25C128 IS25C256 0 0 0 None None 1(1/4) 0 1 3000h 6000h -3FFFh -7FFFh 2(1/2) 1 0 2000h 4000h -3FFFh -7FFFh 3(All) 1 1 0000h 0000h -3FFFh -7FFFh Write Enable (WEN), Bit 1: This bit represents the status of device write protection. If WEN = 0, the Status Register and the entire array is protected from modifica- tion, regardless of the setting of WPEN, WP pin, or block protection. The only way to set WEN to 1 is via the Write Enable command (WREN). WEN is reset to 0 upon power-up. |
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