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IS24C64B-2PI Datasheet(PDF) 5 Page - Integrated Silicon Solution, Inc |
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IS24C64B-2PI Datasheet(HTML) 5 Page - Integrated Silicon Solution, Inc |
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5 / 17 page  Integrated Silicon Solution, Inc. — 1-800-379-4774 5 Rev. A 04/12/06 IS24C32A/B IS24C64A/B ISSI® READ OPERATION Read operations are initiated in the same manner as Write operations, except that the (R/ W) bit of the Slave address is set to “1”. There are three Read operation options: current address read, random address read and sequential read. Current Address Read The IS24CXX contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/ W bit set to “1”), it will respond an ACK and transmit the 8-bit data byte stored ataddresslocationn+1. TheMastershouldnotacknowledge the transfer but should generate a Stop condition so the IS24CXX discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.) Random Address Read Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the IS24CXX acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/ W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.) Sequential Read Sequential Reads can be initiated as either a Current AddressReadorRandomAddressRead. AftertheIS24CXX sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the IS24CXX. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1, n+2 ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of 8191 for IS24C64A/B or 4095 for IS24C32A/B (depending on the device) is reached, the address counter “rolls over” to address 0, and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram). |
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