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IS41LV85120B-60K Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS41LV85120B-60K Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
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4 / 21 page  IS41LV85120B ISSI® 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/22/05 Functional Description The IS41LV85120B is a CMOS DRAM optimized for high- speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 19 address bits. The first ten address bits (A0-A9) are entered as row address and latter nine bits nine address bits (A0-A8) are entered as column address. The row address is latched by the Row Address Strobe ( RAS). The column address is latched by the Column Address Strobe ( CAS). RAS is used to latch the first nine bits and CAS is used the latter nine bits. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time speci- fied by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Refresh Cycle To retain data, 1024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle re- freshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ig- nored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Extended Data Out Page Mode EDO page mode operation permits all 512 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. There- fore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write opera- tions during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the VDD supply, an initial pause of 200 µs is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VDD or be held at a valid VIH to avoid current surges. |
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