1

Rev. 00E

05/18/06

IS42S32200C1

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice.

ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• Clock frequency: 183, 166, 143 MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length:

(1, 2, 4, 8, full page)

• Programmable burst sequence:

Sequential/Interleave

• Self refresh modes

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable

CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

command

• Available in Industrial temperature grade

• Available in 400-mil 86-pin TSOP II and 90-ball

BGA

• Available in Lead free

OVERVIEW

organized as 524,288 bits x 32-bit x 4-bank for improved

performance. The synchronous DRAMs achieve high-

speed data transfer using pipeline architecture. All inputs

and outputs signals refer to the rising edge of the clock

input.

512K Bits x 32 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

PRELIMINARY INFORMATION

MAY 2006

KEY TIMING PARAMETERS

Parameter

-55

-6

-7

Unit

Clk Cycle Time

CAS Latency = 3

5.5

6

7

ns

CAS Latency = 2

10

10

10

ns

Clk Frequency

CAS Latency = 3

183

166

143

Mhz

CAS Latency = 2

100

100

100

Mhz

Access Time from Clock

CAS Latency = 3

5

5.5

5.5

ns

CAS Latency = 2

7.5

7.5

8

ns