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MB90098A Datasheet(PDF) 4 Page - Fujitsu Component Limited. |
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MB90098A Datasheet(HTML) 4 Page - Fujitsu Component Limited. |
4 / 43 page MB90098A 4 s s s s PIN DESCRIPTIONS Pin Pin no. I/O Circuit type Description DCLKI 5 Input B Dot clock input pin DCLKO 22 Output A Dot clock output pin HSYNC 10 Input B Horizontal sync signal input pin. The active level is programmable. VSYNC 11 Input B Vertical sync signal input pin. The active level is programmable. DISP 12 Input B Display output control signal input pin. Input a high level signal to enable display output. Input a low level signal to set the display output (DA3-0, VOBA, DB3-0, VOBB pin output) to inactive level. The active level is programmable. DA3 DA2 DA1 DA0 25 26 27 28 Output A Color signal output pins. In straight output mode, the all-dot signal is output. In demultiplexed output mode, the even dot signal is out- put. The active level is programmable. VOBA 24 Output A Display period signal output pin. In straight output mode, the all- dot display period signal is output. In demultiplexed output mode, the even dot display period signal is output. The active level is pro- grammable. DB3 DB2 DB1 DB0 17 18 19 20 Output A Color signal output pins. In demultiplexed output mode, the odd dot signal is output. In straight output mode, the output is fixed at inactive level. The active level is programmable. VOBB 16 Output A Display period signal output pin. In demultiplexed output mode, the odd dot display period signal is output. In straight output mode, the output is fixed at inactive level. The active level is programmable. BUSY 15 Output A Busy signal output pin. During internal VRAM fill operation, or in- ternal command ROM transfer, a high level signal is output. CS 1 Input C Chip select pin. During serial instruction transfer, a low level signal is input. SIN 2 Input C Serial data input pin. SCLK 3 Input C Shift clock input pin for serial transfer. RESET 13 Input C Reset signal input pin. Input a low level signal at power-on. TEST 14 Input C Test signal input pin. Input a (fixed) high level signal during normal operation. VDD 7, 9, 21 +3.3 V power supply pins. VSS 4, 6, 23 Ground pins TCLKI 8 Input B Test clock input pin. Input a (fixed) low level signal during normal operation. |
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