4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

03/22/06

IS43R16320A

Notes:

1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.

3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type

and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-

ing column address, as shown in Burst Definition.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability

of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR333.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with

clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Burst Definition

Burst Length

Starting Column Address

Order of Accesses Within a Burst

A2

A1

A0

Type = Sequential

Type = Interleaved

2

0

0-1

0-1

11-0

1-0

4

0

0

0-1-2-3

0-1-2-3

0

1

1-2-3-0

1-0-3-2

1

0

2-3-0-1

2-3-0-1

1

1

3-0-1-2

3-2-1-0

8

0

0

0

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-7

0

0

1

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

0

1

0

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

0

1

1

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

1

0

0

4-5-6-7-0-1-2-3

4-5-6-7-0-1-2-3

1

0

1

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

1

1

0

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

1

1

1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0