Integrated Silicon Solution, Inc. — 1-800-379-4774

9

Rev. B

02/03/06

IS61VPD51236A, IS61VPD102418A, IS61LPD51236A, IS61LPD102418A

PARTIAL TRUTH TABLE

Function

GW

GW

GW

GW

GW

BWE

BWE

BWE

BWE

BWE

BWa

BWa

BWa

BWa

BWa

BWb

BWb

BWb

BWb

BWb

BWc

BWc

BWc

BWc

BWc

BWd

BWd

BWd

BWd

BWd

Read

H

H

XXXX

Read

H

L

HHHH

Write Byte 1

H

L

L

H

H

H

Write All Bytes

H

LLLLL

Write All Bytes

L

XXXXX

NEXT CYCLE

ADDRESS

CE

CE

CE

CE

CE

ADSP

ADSP

ADSP

ADSP

ADSP

ADSC

ADSC

ADSC

ADSC

ADSC

ADV

ADV

ADV

ADV

ADV

WRITE

WRITE

WRITE

WRITE

WRITE

OE

OE

OE

OE

OE

DQ

Deselected

None

H

X

L

X

X

X

High-Z

Read, Begin Burst

External

L

L

X

X

X

L

Q

Read, Begin Burst

External

L

L

XXXH

High-Z

Write, Begin Burst

External

L

H

L

X

L

X

D

Read, Begin Burst

External

L

H

L

X

H

L

Q

Read, Begin Burst

External

L

H

L

X

H

H

High-Z

Read, Continue Burst

Next

X

H

H

L

H

L

Q

Read, Continue Burst

Next

X

H

H

L

H

H

High-Z

Read, Continue Burst

Next

H

X

H

L

H

L

Q

Read, Continue Burst

Next

H

X

H

L

H

H

High-Z

Write, Continue Burst

Next

X

H

H

L

L

X

D

Write, Continue Burst

Next

H

X

H

L

L

X

D

Read, Suspend Burst

Current

X

H

H

H

H

L

Q

Read, Suspend Burst

Current

X

H

HHHH

High-Z

Read, Suspend Burst

Current

H

X

H

H

H

L

Q

Read, Suspend Burst

Current

H

X

HHHH

High-Z

Write, Suspend Burst

Current

X

H

H

H

L

X

D

Write, Suspend Burst

Current

H

X

H

H

L

X

D

NOTE:

1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2. For

WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.

WRITE = H for all BWx, BWE, GW HIGH.

3.

BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and

DQPc.

BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and

DQPd are only available on the x36 version.

4. All inputs except

OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation,

OE must be HIGH before the input data setup time and held HIGH during the

input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8.

ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write

enable signals and

BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.